Gate-all-around field effect transistor and method for manufacturing same

ABSTRACT

This application discloses a gate-all-around field effect transistor and a method for manufacturing same. In some implementations the method may include: forming a first fin structure on a substrate, where each first fin structure includes one first laminated structure, where the first laminated structure sequentially includes a sacrificial layer, a support layer, and a channel layer from bottom to top; forming a dummy gate structure across the first fin structure, where the dummy gate structure includes a dummy gate dielectric layer, a dummy gate on the dummy gate dielectric layer, and a first spacer on a side surface of the dummy gate; removing parts of the first fin structure located on two sides of the dummy gate structure, to form a second fin structure; performing first etching on a side surface of the sacrificial layer in the second fin structure, to form a first space; forming a second spacer in the first space; performing second etching on a side surface of the channel layer in the second fin structure, to form a second space; and performing selective epitaxy on the side surface of the channel layer in the second fin structure, to form a source region and a drain region, where along a direction of a channel, compared with a side surface, distal to the sacrificial layer, of the second spacer, the side surface of the channel layer after the second etching is closer to the sacrificial layer.

RELATED APPLICATIONS

The present application claims priority to Chinese Patent Appln. No.201711307799.9, filed Dec. 11, 2017, the entire disclosure of which ishereby incorporated by reference.

BACKGROUND Technical Field

This application relates to the field of semiconductor technologies, andin particular, to a gate-all-around field effect transistor and a methodfor manufacturing the same.

Related Art

For a gate-all-around field effect transistor, only a gate dielectriclayer exists between a gate and a source region and between the gate anda drain region, and there is no effective sidewall or spacer isolation.Consequently, parasitic capacitance is generated.

A solution to the foregoing problem is forming an internal spacerbetween the gate and the drain region and between the gate and thesource region. However, existence of the internal spacer increasesdistances between the source region and the drain region that are formedby means of epitaxy and a channel. Consequently, a stress introducedinto the channel is reduced, leading to on-state current reduction anddevice performance degradation of the gate-all-around field effecttransistor.

SUMMARY

An objective of this application is to increase an on-state current of agate-all-around field effect transistor.

In a first aspect of this application, a method for manufacturing agate-all-around field effect transistor is provided. The method mayinclude: forming a first fin structure on a substrate, where the firstfin structure includes one first laminated structure or a plurality offirst laminated structures stacked, where the first laminated structuresequentially includes a sacrificial layer, a support layer, and achannel layer from bottom to top; forming a dummy gate structure acrossthe first fin structure, where the dummy gate structure includes a dummygate dielectric layer on a surface of the first fin structure, a dummygate on the dummy gate dielectric layer, and a first spacer on a sidesurface of the dummy gate; removing parts of the first fin structurelocated on two sides of the dummy gate structure to form a second finstructure; performing first etching on a side surface of the sacrificiallayer in the second fin structure to form a first space; forming asecond spacer in the first space; performing second etching on a sidesurface of the channel layer in the second fin structure to form asecond space; and after the second space is formed, performing selectiveepitaxy on the side surface of the channel layer in the second finstructure to form a source region and a drain region, where along adirection of a channel, compared with a side surface, distal to thesacrificial layer, of the second spacer, the side surface of the channellayer after the second etching is closer to the sacrificial layer.

In some implementations, forming a second spacer in the first spaceincludes: after the first space is formed, depositing a second spacermaterial, where a part of the second spacer material fills the firstspace; and removing a part of the second spacer material other than thepart of the second spacer material that fills the first space, and usingthe remaining second spacer material as the second spacer.

In some implementations, the first fin structure further includes onesecond laminated structure or a plurality of second laminated structuresstacked on the first laminated structure, where the second laminatedstructure sequentially includes the support layer, the sacrificiallayer, the support layer, and the channel layer from bottom to top.

In some implementations, after the epitaxial region is formed, themethod further includes forming an inter-layer dielectric layer, wherethe inter-layer dielectric layer exposes the dummy gate; removing thedummy gate and the dummy gate dielectric layer to form a first trench;and removing the sacrificial layer and a part of the support layerlocated on the sacrificial layer in the second fin structure to form asecond trench, so as to form the channel layer suspended above thesubstrate.

In some implementations, a part of the support layer located above thesecond spacer is further removed.

In some implementations, the method further includes: forming a gatedielectric layer on a bottom and a sidewall of the second trench and asurface of the channel layer; and after the gate dielectric layer isformed, filling the second trench with a gate.

In some implementations, the channel layer includes a nanowire.

In some implementations, the support layer and the sacrificial layerhave different etching selectivity ratios; and the support layer and thechannel layer have different etching selectivity ratios.

In some implementations, materials of the sacrificial layer and thesupport layer include SiGe; and a material of the channel layer includesSi.

In some implementations, the sacrificial layer and the support layerhave different contents of Ge.

In some implementations, a content of Ge in the sacrificial layer isgreater than a content of Ge in the support layer.

In some implementations, a content of Ge in the sacrificial layer isless than a content of Ge in the support layer.

In another aspect of this application, a gate-all-around field effecttransistor is provided. The gate-all-around field effect transistor mayinclude: one channel layer or a plurality of channel layers separatedfrom each other from bottom to top above a substrate; a gate structureall around the channel layer, where the gate structure sequentiallyincludes a first gate dielectric layer and a gate from inside tooutside; a source region and a drain region, located on two sides of thegate structure and formed by performing epitaxy on a side surface of thechannel layer; a second gate dielectric layer, located between the gateand the source region and between the gate and the drain region; and aspacer, located between the second gate dielectric layer and the sourceregion and between the second gate dielectric layer and the drainregion, where along a direction of a channel, compared with a sidesurface, distal to the gate, of the spacer, the side surface of thechannel layer is closer to the gate.

In some implementations, the channel layer includes a nanowire.

In some implementations, the field effect transistor further includes athird gate dielectric layer, located between an upper surface of thespacer and the source region and between the upper surface of the spacerand the drain region.

In embodiments and forms of the present disclosure, on one hand, thesecond spacer is formed so that parasitic capacitance can be reduced. Onthe other hand, along the direction of the channel, compared with theside surface, distal to the sacrificial layer, of the second spacer, theside surface of the channel layer after the second etching is closer tothe sacrificial layer, so that the side surface of the channel layer iscloser to the gate formed after the sacrificial layer is removed,thereby increasing an on-state current of a gate-all-around field effecttransistor.

Exemplary embodiments and forms of the present disclosure are describedbelow in detail with reference to accompanying drawings, so as to makeother features, aspects, and advantages of this application clear.

BRIEF DESCRIPTION OF THE DRAWINGS

Accompanying drawings that constitute a part of the specificationdescribe exemplary embodiments and implementations of this applicationand are used, together with the specification, to explain the principlesof this application, wherein:

FIG. 1 is a simplified flowchart of a method for manufacturing agate-all-around field effect transistor;

FIG. 2A shows a schematic cross-sectional diagram along a direction of achannel of a stage of a method for manufacturing a gate-all-around fieldeffect transistor;

FIG. 2B shows a schematic cross-sectional diagram along a directionperpendicular to the direction of the channel of the stage shown in FIG.2A;

FIG. 3A shows a schematic cross-sectional diagram along a direction of achannel of a stage of a method for manufacturing a gate-all-around fieldeffect transistor;

FIG. 3B shows a schematic cross-sectional diagram along a directionperpendicular to the direction of the channel of the stage shown in FIG.3A;

FIG. 4A shows a schematic cross-sectional diagram along a direction of achannel of a stage of a method for manufacturing a gate-all-around fieldeffect transistor;

FIG. 4B shows a schematic cross-sectional diagram along a directionperpendicular to the direction of the channel of the stage shown in FIG.4A;

FIG. 5A shows a schematic cross-sectional diagram along a direction of achannel of a stage of a method for manufacturing a gate-all-around fieldeffect transistor;

FIG. 5B shows a schematic cross-sectional diagram along a directionperpendicular to the direction of the channel of the stage shown in FIG.5A;

FIG. 6A shows a schematic cross-sectional diagram along a direction of achannel of a stage of a method for manufacturing a gate-all-around fieldeffect transistor;

FIG. 6B shows a schematic cross-sectional diagram along a directionperpendicular to the direction of the channel of the stage shown in FIG.6A;

FIG. 7A shows a schematic cross-sectional diagram along a direction of achannel of a stage of a method for manufacturing a gate-all-around fieldeffect transistor;

FIG. 7B shows a schematic cross-sectional diagram along a directionperpendicular to the direction of the channel of the stage shown in FIG.7A;

FIG. 8A shows a schematic cross-sectional diagram along a direction of achannel of a stage of a method for manufacturing a gate-all-around fieldeffect transistor;

FIG. 8B shows a schematic cross-sectional diagram along a directionperpendicular to the direction of the channel of the stage shown in FIG.8A;

FIG. 9A shows a schematic cross-sectional diagram along a direction of achannel of a stage of a method for manufacturing a gate-all-around fieldeffect transistor;

FIG. 9B shows a schematic cross-sectional diagram along a directionperpendicular to the direction of the channel of the stage shown in FIG.9A;

FIG. 10A shows a schematic cross-sectional diagram along a direction ofa channel of a stage of a method for manufacturing a gate-all-aroundfield effect transistor;

FIG. 10B shows a schematic cross-sectional diagram along a directionperpendicular to the direction of the channel of the stage shown in FIG.10A;

FIG. 11A shows a schematic cross-sectional diagram along a direction ofa channel of a stage of a method for manufacturing a gate-all-aroundfield effect transistor;

FIG. 11B shows a schematic cross-sectional diagram along a directionperpendicular to the direction of the channel of the stage shown in FIG.11A;

FIG. 12A shows a schematic cross-sectional diagram along a direction ofa channel of a stage of a method for manufacturing a gate-all-aroundfield effect transistor;

FIG. 12B shows a schematic cross-sectional diagram along a directionperpendicular to the direction of the channel of the stage shown in FIG.12A;

FIG. 13A shows a schematic cross-sectional diagram along a direction ofa channel of a stage of a method for manufacturing a gate-all-aroundfield effect transistor;

FIG. 13B shows a schematic cross-sectional diagram along a directionperpendicular to the direction of the channel of the stage shown in FIG.13A;

FIG. 14A shows a schematic cross-sectional diagram along a direction ofa channel of a stage of a method for manufacturing a gate-all-aroundfield effect transistor;

FIG. 14B shows a schematic cross-sectional diagram along a directionperpendicular to the direction of the channel of the stage shown in FIG.14A;

FIG. 15A shows a schematic cross-sectional diagram along a direction ofa channel of a gate-all-around field effect transistor; and

FIG. 15B shows a schematic cross-sectional diagram along a directionperpendicular to the direction of the channel of the gate-all-aroundfield effect transistor shown in FIG. 15A.

DETAILED DESCRIPTION

Various exemplary embodiments and implementations of the presentdisclosure are described now in detail with reference to theaccompanying drawings. It should be understood that unless otherwisespecified, the relative disposition, numerical expressions, andnumerical values of the components and steps described in theembodiments and implementations should not be understood as limitationsto the scope of this application.

Meanwhile, it should be understood that to facilitate description, sizesof components in the drawings do not need to be drawn according to theactual proportional relationships. For example, the thicknesses orwidths of some layers can be enlarged with respect to other layers.

The following descriptions on the exemplary embodiments andimplementations are merely illustrative and shall never serve aslimitations to this application and its application or use thereof.

The technologies, methods, and apparatuses known by a person of ordinaryskill in the art may be not discussed in detail, but in a situation towhich technologies, methods, and apparatuses are applicable, thetechnologies, methods, and apparatuses shall be considered as a part ofthe specification.

It should be noted that similar reference signs and letters representsimilar items in the following accompanying drawings. Therefore, once aspecific item is defined or described in one accompanying drawing, it isunnecessary to further discuss the item in descriptions on subsequentaccompanying drawings.

FIG. 1 is a simplified flowchart of a method for manufacturing agate-all-around field effect transistor.

FIG. 2A to FIG. 9B show schematic cross-sectional diagrams of stages ofa method for manufacturing a gate-all-around field effect transistor.FIG. 2A, FIG. 3A, . . . , and FIG. 9A are schematic cross-sectionaldiagrams along a direction of a channel (also referred to as ahorizontal direction) of stages of a method for manufacturing agate-all-around field effect transistor. FIG. 2B, FIG. 3B, . . . , andFIG. 9B are respectively schematic cross-sectional diagrams along adirection perpendicular to the direction of the channel (also referredto as a vertical direction) of the stages shown in FIG. 2A, FIG. 3A, . .. , and FIG. 9A.

As shown in FIG. 1, first, in step 102, a first fin structure is formedon a substrate 200.

As shown in FIG. 2A and FIG. 2B, the first fin structure may include afirst laminated structure 201. The first laminated structure 201 maysequentially include a sacrificial layer 211, a support layer 221, and achannel layer 231 from bottom to top. In some implementations, thechannel layer 231 may be a nanowire. It should be understood thatalthough FIG. 2A and FIG. 2B show only one first laminated structure201, this application is not limited thereto. In other implementations,the first fin structure may include a plurality of first laminatedstructures 201, and the plurality of first laminated structures 201 issequentially stacked on the substrate 200 from bottom to top.

The substrate 200 may be, for example, a semiconductor substrate of anelement such as silicon or germanium, or a semiconductor substrate of acompound such as gallium arsenide. Materials of the sacrificial layer211, the support layer 221, and the channel layer 231 may be, forexample, a semiconductor material such as Si, SiGe, Ge, or a group III-Vsemiconductor material.

In some implementations, the support layer 221 and the sacrificial layer211 have different etching selectivity ratios; and the support layer 221and the channel layer 231 have different etching selectivity ratios. Asan example, materials of the sacrificial layer 211 and the support layer221 may include SiGe; and a material of the channel layer 231 mayinclude Si. In an implementation, the sacrificial layer 211 and thesupport layer 221 have different contents of Ge. For example, a contentof Ge in the sacrificial layer 211 may be greater than a content of Gein the support layer 221. For another example, a content of Ge in thesacrificial layer 211 may be less than a content of Ge in the supportlayer 221.

In some implementations, a sacrificial material layer, a supportmaterial layer, and a channel material layer may be sequentially formedon the substrate 200 by means of epitaxy. Subsequently, the sacrificialmaterial layer, the support material layer, and the channel materiallayer are patterned, so as to form a first fin structure including thefirst laminated structure 201.

As an example, the thickness of the support layer 221 ranges fromapproximately 1 nm to 5 nm, for example, is 2 nm, 4 nm, or the like. Asan example, the thickness of the sacrificial layer 211 ranges fromapproximately 2 nm to 20 nm, for example, is 5 nm, 10 nm, 15 nm, or thelike.

In some implementations, referring to FIG. 2A and FIG. 2B, the first finstructure may further include one second laminated structure 202 or aplurality of second laminated structures 202 stacked on the firstlaminated structure 201. The second laminated structure 202 maysequentially include the support layer 221, the sacrificial layer 211,the support layer 221, and the channel layer 231 from bottom to top. Itshould be understood that although FIG. 2A and FIG. 2B illustrativelyshow two second laminated structures 202 stacked, they are notlimitative. In other implementations, the first fin structure mayalternatively include one, three, four, or more second laminatedstructures 202. Alternatively, the first laminated structures 201 andthe second laminated structures 202 in the first fin structure may bearranged alternately.

Referring to FIG. 1 again, subsequently, in step 104, a dummy gatestructure 301 across the first fin structure is formed.

As shown in FIG. 3A and FIG. 3B, the dummy gate structure 301 mayinclude a dummy gate dielectric layer 311 on a surface (including anupper surface and a side surface) of the first fin structure, a dummygate 321 on the dummy gate dielectric layer 311, and a first spacer 331on a side surface of the dummy gate 321. Illustratively, a material ofthe dummy gate 321 may be, for example, polysilicon, a material of thedummy gate dielectric layer 311 may be, for example, an oxide ofsilicon, and a material of a hard mask layer 341 may typically be anitride of silicon, an oxide of silicon, a nitrogen oxide of silicon, orthe like.

In some implementations, the dummy gate structure 301 may furtherinclude a hard mask layer 341, for example, a nitride of silicon, on thedummy gate 321. It should be understood that the first spacer 331 mayalternatively be located on side surfaces of the dummy gate dielectriclayer 311 and the hard mask layer 341. It should also be understood thata part of the dummy gate dielectric layer 311 may also be located on thesubstrate 200.

In an implementation, the dummy gate structure 301 may be formed in thefollowing manner: first, sequentially depositing a dummy gate dielectricmaterial layer and a dummy gate material layer on a surface of astructure shown in FIG. 2A and FIG. 2B; then, forming the patterned hardmask layer 341 on the dummy gate material layer; subsequently,patterning the dummy gate dielectric material layer and the dummy gatematerial layer using the hard mask layer 341 as a mask, so as to formthe dummy gate dielectric layer 311 and the dummy gate 321; and then,forming the first spacer 331 on two sides of the dummy gate dielectriclayer 311 and two sides of the dummy gate 321, so as to form the dummygate structure 301.

Referring to FIG. 1, in step 106, parts of the first fin structurelocated on two sides of the dummy gate structure 301 are removed to forma second fin structure 401 (that is, the remaining part of the first finstructure), as shown in FIG. 4A and FIG. 4B. For example, the parts ofthe first fin structure located on the two sides of the dummy gatestructure 301 may be removed by means of dry etching.

Subsequently, in step 108, first etching such as wet etching isperformed on a side surface of the sacrificial layer 211 in the secondfin structure 401 to form a first space 501, as shown in FIG. 5A andFIG. 5B. For example, the side surface of the sacrificial layer 211after the first etching may be essentially aligned with adjacentinterfaces of the first spacer 321 and the dummy gate 321 (as shown inFIG. 5A). In another example, the side surface of the sacrificial layer211 after the first etching may be located below the first spacer 331,that is, the first space 501 is smaller than that shown in FIG. 5A. Thedepth of the first space 501 along a direction of a channel ranges fromapproximately 5 nm to 20 nm, for example, such as 10 nm, 15 nm, or thelike.

Subsequently, in step 110, a second spacer 701 is formed in the firstspace 501. The size of the second spacer 701 along the direction of thechannel ranges from approximately 5 nm to 20 nm, for example, such as 10nm, 15 nm, or the like.

As shown in FIG. 6A and FIG. 6B, after the first space 501 is formed, asecond spacer material 601 such as an oxide of silicon is deposited. Apart of the second spacer material 601 fills the first space 501.

As shown in FIG. 7A and FIG. 7B, for example, a part of the secondspacer material 601 other than the part of the second spacer material601 that fills the first space 501 may be removed by means ofanisotropic etching, and the remaining second spacer material 601 isused as the second spacer 701.

Subsequently, in step 112, second etching is performed on a side surfaceof the channel layer 231 in the second fin structure 401, to form asecond space 801, as shown in FIG. 8A and FIG. 8B. For example, the sidesurface of the channel layer 231 after the second etching may beessentially aligned with adjacent interfaces of the first spacer 321 andthe dummy gate 321 (as shown in FIG. 8A). For another example, the sidesurface of the channel layer 231 after the second etching may be locatedbelow the first spacer 331, that is, the second space 801 is smallerthan that shown in FIG. 8A.

Subsequently, in step 114, after the second space 801 is formed,selective epitaxy is performed on the side surface of the channel layer231 in the second fin structure 401, to form a source region 901 and adrain region 902, as shown in FIG. 9A and FIG. 9B. Herein, along adirection of a channel, compared with a side surface, distal to thesacrificial layer 211, of the second spacer 701, the side surface of thechannel layer 231 after the second etching is closer to the sacrificiallayer 211. For example, the side surface of the channel layer 231 afterthe second etching may be above the second spacer 701. For anotherexample, the side surface of the channel layer 231 after the secondetching is essentially aligned with the side surface of the sacrificiallayer 211.

In implementations of the manufacturing method described above, on onehand, the second spacer is formed so that parasitic capacitance can bereduced. On the other hand, along the direction of the channel, comparedwith the side surface, distal to the sacrificial layer, of the secondspacer, the side surface of the channel layer after the second etchingis closer to the sacrificial layer so that the side surface of thechannel layer is closer to the gate formed after the sacrificial layeris removed, thereby increasing an on-state current of a gate-all-aroundfield effect transistor.

Subsequently, the dummy gate structure may be replaced with a gatestructure such as a high-k metal gate stack structure.

A process of replacing the dummy gate structure with the gate structureis described below with reference to FIG. 10A to FIG. 14B. It should benoted that the following process is not limited to being performed inthe same embodiment.

As shown in FIG. 10A and FIG. 10B, an inter-layer dielectric layer 1001is formed. The inter-layer dielectric layer 1001 herein may expose thedummy gate 331. For example, an inter-layer dielectric material layersuch as an oxide of silicon may be deposited on a structure shown inFIG. 9A and FIG. 9B, and then, a planarization process is performed toexpose the dummy gate 331. It should be understood that if a hard masklayer 341 exists on the dummy gate 321, the hard mask layer 341 is alsoremoved in the planarization process.

First, as shown in FIG. 11A and FIG. 11B, the dummy gate 321 and thedummy gate dielectric layer 311 are removed, to form a first trench1101. Herein, the first trench 1101 may be also referred to as a gap ora space formed after the dummy gate 321 and the dummy gate dielectriclayer 311 are removed.

Subsequently, in an implementation, as shown in FIG. 12A and FIG. 12B,the sacrificial layer 211 and the support layer 221 (including a partlocated above the sacrificial layer 211 and a part located above thesecond spacer 701) in the second fin structure 401 are removed to form asecond trench 1201, so as to form the channel layer 231 suspended abovethe substrate 200. In some implementations, the channel layer 231 may bea nanowire. It should be understood that the second trench 1201 hereinmay also be referred to as a gap or a space formed after the dummy gate321, the dummy gate dielectric layer 311, and the sacrificial layer 211and the support layer 221 in the second fin structure 401 are removed.

In other implementations, as shown in FIG. 13A and FIG. 13B, when thesecond trench 1201 is formed, the sacrificial layer 211 and the part ofthe support layer 221 located above the sacrificial layer 211 in thesecond fin structure 401 may be removed, for example, by means of atomiclayer etching (ALE), and the part of the support layer 221 located abovethe second spacer 701 may be partially or entirely reserved, so as toform the channel layer 231 suspended above the substrate 200. It shouldbe understood that the second trench 1201 herein may also be referred toas a gap or a space formed after the dummy gate 321, the dummy gatedielectric layer 311, and the sacrificial layer 211 and the part of thesupport layer 221 located above the sacrificial layer 211 in the secondfin structure 401 are removed.

As shown in FIG. 14A and FIG. 14B, a gate dielectric layer 1301 such asa high-k dielectric layer of HfO₂ is formed on a bottom and a sidewallof the second trench 1201 and a surface of the channel layer 231. Afterthe gate dielectric layer 1301 is formed, a gate 1302 such as a metalgate filling the second trench 1201 is formed. In some implementations,before the gate dielectric layer 1301 is formed, an interface layer suchas an oxide of silicon layer may be first formed on the bottom and thesidewall of the second trench 1201 and the surface of the channel layer231, so as to improve interface characteristics between the bottom andthe sidewall of the second trench 1201 and the gate dielectric layer1301 and between the surface of the channel layer 231 and the gatedielectric layer 1301, to improve a binding force.

It should be understood that after the dummy gate 321, the dummy gatedielectric layer 311, and the sacrificial layer 211 and the supportlayer 221 in the second fin structure 401 are removed, surfaces of someregions are exposed. For example, some parts of a surface of thesubstrate 200, some parts of surfaces of the source region 901 and thedrain region 902, some parts of a surface of the second spacer 701, anda surface of the channel layer 231 are exposed. Moreover, an interfacelayer (if it exists) and the gate dielectric layer 1301 may besequentially formed on the exposed surfaces. Therefore, in this sense,the bottom of the second trench 1201 may be also referred to as anexposed surface of the substrate 200, and the sidewall of the secondtrench 1201 may be also referred to as exposed surfaces of the sourceregion 901 and the drain region 902 and an exposed surface of the secondspacer 701.

After the gate 1302 is formed, referring to FIG. 14A, along a directionof a channel, compared with a side surface, distal to the gate 1302, ofthe second spacer 701, the side surface of the channel layer 231 iscloser to the gate 1302, so that the source region 901 and the drainregion 902 that are adjacent to the channel layer 231 may introduce agreater stress to the channel layer 231, thereby increasing an on-statecurrent of a gate-all-around field effect transistor.

This application further provides a gate-all-around field effecttransistor, which may be, but not limited to being, manufactured usingthe foregoing manufacturing method.

Referring to FIG. 15A and FIG. 15B, the gate-all-around field effecttransistor may include:

one channel layer 231 or a plurality of channel layers 231 such asnanowires separated from each other from bottom to top above a substrate200;

a gate structure all around the channel layer 231, where the gatestructure herein may sequentially include a first gate dielectric layer(a part of the gate dielectric layer 1301 around the channel layer 231,that is, a part of the gate dielectric layer 1301 enclosed by an ellipse1401) and a gate 1302 from inside to outside;

a source region 901 and a drain region 902, located on two sides of thegate structure and formed by performing epitaxy on a side surface of thechannel layer 231;

a second gate dielectric layer, located between the gate 1302 and thesource region 901 and between the gate 1302 and the drain region 901 (apart of the gate dielectric layer 1301 located above the second spacer701 and facing a side surface of the gate 1302, that is, a part of thegate dielectric layer 1301 enclosed by an ellipse 1402); and

a spacer 701 (corresponding to the second spacer 701), located betweenthe second gate dielectric layer and the source region 901 and betweenthe second gate dielectric layer and the drain region 902.

Along a direction of a channel, compared with a side surface 711, distalto the gate 1302, of the spacer 701, the side surface (that is, adjacentinterfaces of the source region 901/drain region 902 and the channellayer 231) of the channel layer 231 is closer to the gate 1302.

In some implementations, the gate-all-around field effect transistor mayfurther include a third gate dielectric layer, located between an uppersurface of the spacer 701 and the source region 901 and between theupper surface of the spacer 701 and the drain region 902.

So far, the gate-all-around field effect transistor and a method formanufacturing same according to the embodiments of this application havebeen described in detail. To prevent overshadowing the ideas of thisapplication, some well-known details in the art are not described.According to the foregoing descriptions, a person skilled in the artwill understand how to carry out the technical solutions disclosedherein. In addition, the embodiments and implementations taught by thedisclosure of this specification can be freely combined. It should beunderstood by a person skilled in the art that various modifications maybe made on the embodiments described above without departing from thespirit and scope of this application defined in the appended claims.

What is claimed is:
 1. A method for manufacturing a gate-all-aroundfield effect transistor, comprising: forming a first fin structure on asubstrate, wherein the first fin structure comprises one first laminatedstructure or a plurality of first stacked laminated structures, whereineach first laminated structure sequentially comprises a sacrificiallayer, a support layer, and a channel layer from bottom to top; forminga dummy gate structure across the first fin structure, wherein the dummygate structure comprises a dummy gate dielectric layer on a surface ofthe first fin structure, a dummy gate on the dummy gate dielectriclayer, and a first spacer on a side surface of the dummy gate; removingparts of the first fin structure located on two sides of the dummy gatestructure to form a second fin structure; performing first etching on aside surface of the sacrificial layer in the second fin structure toform a first space; forming a second spacer in the first space;performing second etching on a side surface of the channel layer in thesecond fin structure to form a second space; and after the second spaceis formed, performing selective epitaxy on the side surface of thechannel layer in the second fin structure to form a source region and adrain region; wherein along a direction of a channel, compared with aside surface, distal to the sacrificial layer, of the second spacer, theside surface of the channel layer after the second etching is closer tothe sacrificial layer.
 2. The method according to claim 1, whereinforming a second spacer in the first space comprises: after the firstspace is formed, depositing a second spacer material, wherein a part ofthe second spacer material fills the first space; and removing a part ofthe second spacer material other than the part of the second spacermaterial that fills the first space, and using the remaining secondspacer material as the second spacer.
 3. The method according to claim1, wherein the first fin structure further comprises one secondlaminated structure or a plurality of second laminated structuresstacked on the first laminated structure, wherein each second laminatedstructure sequentially comprises a second support layer, a secondsacrificial layer, a third support layer, and a second channel layerfrom bottom to top.
 4. The method according to claim 1, wherein afterthe selective epitaxy is performed and an epitaxial region is formedthereby, the method further comprises: forming an inter-layer dielectriclayer, wherein the inter-layer dielectric layer exposes the dummy gate;removing the dummy gate and the dummy gate dielectric layer to form afirst trench; and removing the sacrificial layer and a part of thesupport layer located on the sacrificial layer in the second finstructure to form a second trench, so as to make the channel layer besuspended above the substrate.
 5. The method according to claim 4,wherein a second part of the support layer located above the secondspacer is further removed.
 6. The method according to claim 4, furthercomprising: forming a gate dielectric layer on a bottom and a sidewallof the second trench and a surface of the channel layer; and after thegate dielectric layer is formed, filling the second trench with a gate.7. The method according to claim 1, wherein the channel layer comprisesa nanowire.
 8. The method according to claim 1, wherein: the supportlayer and the sacrificial layer have different etching selectivityratios; and the support layer and the channel layer have differentetching selectivity ratios.
 9. The method according to claim 8, wherein:materials of the sacrificial layer and the support layer comprise SiGe;and a material of the channel layer comprises Si.
 10. The methodaccording to claim 9, wherein the sacrificial layer and the supportlayer have different contents of Ge.